Systemverilog rtl model for 4-bit johnson counter

Develop SystemVerilog RTL model for 4-bit Johnson Counter and perform following mentioned :

§ Synthesize Johnson counter

§ Run simulation using Johnson counter testbench provided

§ Review synthesis results (resource usage and RTL netlist/schematic)

o Note : Explanation of resource usage in report is not mandatory to provide.

§ Review input and output signals in simulation waveform.

Submit report (PDF file) which should include:

§ SystemVerilog design and testbench code

§ Synthesis resource usage and schematic generated from RTL netlist viewer

§ Simulation snapshot and explain simulation result to confirm it works as a Johnson counter

§ Resource usage explanation and post mapping schematic is optional to submit.


§ When creating RTL model for Johnson Counter, name SystemVerilog Module name as : johnson_counter

§ Assume below mentioned Primary Ports for Johnson Counter

o Input clk (clock)

o Input clear (asynchronous reset / negedge signal)

o Input preset (synchronous and active low singal)

o Input load_cnt (value gets loaded when !preset)

o Output  count (output count value)

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